网站做标签页,wordpress mu 搜索,北京各大公司名称,重庆网站建设的培训机构PS#xff1a;升腾A7pro系列FPGA没有数码管外设#xff0c;因此以AC620FPGA为例展开实验。
#xff08;1#xff09;共阳极数码管和共阴极数码管示意图#xff1a; AC620中的数码管属于共阳极数码管#xff0c;段选端口(dp,g,f,e,d,c,b,a)低电平即可点亮led。人眼的视觉…PS升腾A7pro系列FPGA没有数码管外设因此以AC620FPGA为例展开实验。
1共阳极数码管和共阴极数码管示意图 AC620中的数码管属于共阳极数码管段选端口(dp,g,f,e,d,c,b,a)低电平即可点亮led。人眼的视觉停留效应当led以小于20ms的时间间隔进行闪烁时在人眼看来就是一直亮着的。预使8个数码管实现动态扫描的效果需要扫描间隔小于20ms/8 2.5ms不妨取1ms。第一毫秒位选sel[0]高电平其余sel[0:6]低电平第二毫秒位选sel[1]高电平其余sel[0]、sel[2:6]低电平依次循环。
2段选、位选Verilog代码
module hex(clk,reset_n,data,sel,seg);input clk;
input reset_n;
input [31:0]data;output reg[7:0]sel;
output reg[7:0]seg;//1ms 1_000_000ns 20ns * 50_000;
reg [15:0]cnt;
reg [2:0]sel_cnt;
reg [3:0]temp_data;
reg [7:0]r_sel;parameter MCNT 49_999;//1ms计数器模块
always(posedge clk or negedge reset_n)if(!reset_n)cnt 16d0;else if(cnt MCNT)cnt 16d0;else cnt cnt 16d1;//sel_cnt计数器模块设计
always(posedge clk or negedge reset_n)if(!reset_n)sel_cnt 3d0;else if(cnt MCNT)sel_cnt sel_cnt 3d1;else sel_cnt sel_cnt;//r_sel信号设计
always(posedge clk or negedge reset_n)if(!reset_n)r_sel 8h01;else begincase(sel_cnt)3d0: r_sel 8h01;3d1: r_sel 8h02;3d2: r_sel 8h04;3d3: r_sel 8h08;3d4: r_sel 8h10;3d5: r_sel 8h20;3d6: r_sel 8h40;3d7: r_sel 8h80;endcaseend//sel信号设计 打一拍的目的是为了和seg信号同步
always(posedge clk)sel r_sel;//temp_data信号设计
always(posedge clk or negedge reset_n)if(!reset_n)temp_data 4d0;else begincase(sel_cnt)3d0:temp_data data[3:0];3d1:temp_data data[7:4];3d2:temp_data data[11:8];3d3:temp_data data[15:12];3d4:temp_data data[19:16];3d5:temp_data data[23:20];3d6:temp_data data[27:24];3d7:temp_data data[31:28];endcaseend//seg信号设计
always(posedge clk or negedge reset_n)if(!reset_n)seg 8hff;else begincase(temp_data)4h0:seg 8b1100_0000;4h1:seg 8b1111_1001;4h2:seg 8b1010_0100;4h3:seg 8b1011_0000;4h4:seg 8b1001_1001;4h5:seg 8b1001_0010;4h6:seg 8b1000_0010;4h7:seg 8b1111_1000;4h8:seg 8b1000_0000;4h9:seg 8b1001_0000;4ha:seg 8b1000_1000;4hb:seg 8b1000_0011;4hc:seg 8b1100_0110;4hd:seg 8b1010_0001;4he:seg 8b1000_0110;4hf:seg 8b1000_1110;endcaseendendmodule3对应仿真文件代码
timescale 1ns/1nsmodule hex_tb;reg clk;reg reset_n;reg [31:0]data;wire [7:0]sel;wire [7:0]seg;hex hex_inst(.clk(clk),.reset_n(reset_n),.data(data),.sel(sel),.seg(seg));defparam hex_inst.MCNT 499;initial clk 1d1;always #10 clk ~clk;initial beginreset_n 1d0;#25;reset_n 1d1;#15;data 32h00112233;#200_000;data 32h44556677;#200_000;data 32h8899aabb;#200_000;data 32hccddeeff;#200_000;$stop;endendmodule4仿真波形: 574HC595芯片:
74HC595芯片内部工作原理 先传段选再传位选先传高位再传低位。(段位高低)74HC595芯片在3.3v工作电压下可以承受的工作频率为12.5MHz。 (6)74HC595驱动代码
module hc595_driver(clk,reset_n,sel,seg,DIO,SCLK,RCLK);input clk;
input reset_n;
input [7:0]sel;
input [7:0]seg;output reg DIO;
output reg SCLK;
output reg RCLK;//74HC595芯片在3.3v工作电压下可以承受的工作频率为12.5MHz对应一个周期为80ns半个周期为两个系统时钟周期
reg div_cnt;
reg [4:0]bit_cnt;//分频计数器设计
always(posedge clk or negedge reset_n)if(!reset_n)div_cnt 1d0;else div_cnt div_cnt 1d1;//bit_cnt设计
always(posedge clk or negedge reset_n)if(!reset_n)bit_cnt 5d0;else if(div_cnt 1d1)bit_cnt bit_cnt 5d1;else bit_cnt bit_cnt;//序列机设计
always(posedge clk or negedge reset_n)if(!reset_n)beginDIO 1d0;RCLK 1d0;SCLK 1d0;endelse if(div_cnt 1d1)begincase(bit_cnt)5d0: begin DIO seg[7];SCLK 1d0;RCLK 1d1;end5d1: begin SCLK 1d1;RCLK 1d0;end5d2: begin DIO seg[6];SCLK 1d0;end5d3: begin SCLK 1d1;end5d4: begin DIO seg[5];SCLK 1d0;end5d5: begin SCLK 1d1;end5d6: begin DIO seg[4];SCLK 1d0;end5d7: begin SCLK 1d1;end5d8: begin DIO seg[3];SCLK 1d0;end5d9: begin SCLK 1d1;end5d10:begin DIO seg[2];SCLK 1d0;end5d11:begin SCLK 1d1;end5d12:begin DIO seg[1];SCLK 1d0;end5d13:begin SCLK 1d1;end5d14:begin DIO seg[0];SCLK 1d0;end5d15:begin SCLK 1d1;end5d16:begin DIO sel[7];SCLK 1d0;end5d17:begin SCLK 1d1;end5d18:begin DIO sel[6];SCLK 1d0;end5d19:begin SCLK 1d1;end5d20:begin DIO sel[5];SCLK 1d0;end5d21:begin SCLK 1d1;end5d22:begin DIO sel[4];SCLK 1d0;end5d23:begin SCLK 1d1;end5d24:begin DIO sel[3];SCLK 1d0;end5d25:begin SCLK 1d1;end5d26:begin DIO sel[2];SCLK 1d0;end5d27:begin SCLK 1d1;end5d28:begin DIO sel[1];SCLK 1d0;end5d29:begin SCLK 1d1;end5d30:begin DIO sel[0];SCLK 1d0;end5d31:begin SCLK 1d1;endendcaseendelse beginDIO DIO;RCLK RCLK;SCLK SCLK;endendmodule(7)顶层代码
module hex_top(clk,reset_n,sw,DIO,SCLK,RCLK);input clk;input reset_n;input [3:0]sw;output DIO;output SCLK;output RCLK;reg [31:0]data;wire [7:0]sel;wire [7:0]seg;hex hex_inst(.clk(clk),.reset_n(reset_n),.data(data),.sel(sel),.seg(seg));hc595_driver hc595_driver_inst(.clk(clk),.reset_n(reset_n),.sel(sel),.seg(seg),.DIO(DIO),.SCLK(SCLK),.RCLK(RCLK));//data设计always(posedge clk or negedge reset_n)if(!reset_n)data 32d0;else begincase(sw)4h1:data 32h76543210;4h2:data 32hfedcba98;4h4:data 32h98765432;4h8:data 32h12345678;default:data 32h00000000;endcaseendendmodule8引脚绑定:
